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S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN
11
GA1085
S1
10
REFCLK
9
S0
8
F1
7
F0
6
GND
5
TEST 12 VDD 13
Phase Detector VCO Phase Select
4 VDD 3 2
Q10 Q9
11-Output Configurable Clock Buffer
Q0
14
GND 15 Q1 Q2
16 17
MUX Divide Logic /4, /5, or /6 Output Buffers Group A Group C
1 GND 28 27
Q8 Q7
Features
* Wide frequency range: 24 MHz to 105 MHz * Output configurations: Four outputs at fREF Four outputs at fREF /2 Two outputs at fREF /2 with adjustable phase or Five outputs at 2x fREF Three outputs at fREF Two outputs at fREF with adjustable phase * Selectable Phase Shift: -2t, -t, +t, and +2t (t = 1/fVCO) * Low output-to-output skew: 150 ps (max) within a group * Near-zero propagation delay: -350 ps +1000 ps (max) * TTL-compatible with 30 mA output drive * 28-pin J-lead surface-mount package
VDD 18
Group B
26 VDD
19
20
21
22
23
24
25
GND
Q3
Q4
VDD
Q5
Q6
GND
TriQuint's GA1085 is a configurable clock buffer which generates 11 outputs and operates over a wide range of frequencies--from 24 MHz to 105 MHz. The outputs are available at either 1x and 2x or at 1x and 1/2 x the reference clock frequency, fREF. When one of the Group A outputs (Q4-Q8) is used as feedback to the PLL, all Group A outputs will be at fREF , and all Group B (Q0-Q3) and Group C (Q9, Q10) outputs will be at 1/2 x fREF . When one of the Group B outputs is used as feedback to the PLL, all Group A outputs will be at 2x REF and all Group B and Group C outputs will be at fREF . The Shift Select pins select the phase shift (-2t, -t, +t or +2t) for Group C outputs (Q9, Q10) with respect to REFCLK. The phase shift increment (t) is equivalent to the VCO's period (1/fVCO). A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation. This completely self-contained PLL requires no external capacitors or resistors. The PLL's Voltage-Controlled Oscillator (VCO) has a frequency range from 280 MHz to 420 MHz. By feeding back one of the output clocks to FBIN, the PLL continuously maintains frequency and phase synchron-ization between the reference clock (REFCLK) and each of the outputs. TriQuint's patented output buffer design delivers a very low output-to-output skew of 150 ps (max). The GA1085's symmetrical TTL outputs are capable of sourcing and sinking 30 mA.
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1
SYSTEM TIMING PRODUCTS SYSTEMS TIMING
GA1085
Functional Description
The core of the GA1085 is a Phase-Locked Loop (PLL) that continuously compares the reference clock (REFCLK) to the feedback clock (FBIN), maintaining a zero frequency difference between the two. Since one of the outputs (Q0-Q8) is always connected to FBIN, the PLL keeps the propagation delay between the outputs and the reference clock within -350 ps +1000 ps. The internal Voltage-Controlled Oscillator (VCO) has an operating range of 280 MHz to 420 MHz. The combination of the VCO and the Divide Logic enables the GA1085 to operate between 24 MHz and 105 MHz. The device features six divide modes: /4, /5, /6, /8, /10, and /12. The Frequency Select pins, F0 and F1, and the output used as feedback to FBIN set the divide mode as shown in Table 1. The Shift Select pins, S0 and S1, control the phase shift of Q9 and Q10 relative to the other outputs. The user can select from four incremental phase shifts as shown in Table 2.
The phase-shift increment (t) is calculated using the following equation:
t=
1 (f REF) (n)
where n is the divide mode. In the test mode, the PLL is bypassed and REFCLK is connected directly to the Divide Logic block via the MUX, as shown in Figure 1. This mode is useful for debug and test purposes. The various test modes are outlined in Table 3. In the test mode, the frequency of the reference clock is divided by 4, 5, or 6. The maximum rise and fall time at the output pins is 1.4 ns. All outputs of the GA1085 are TTL-compatible with 30 mA symmetric drive and a minimum VOH of 2.4 V.
Power-Up/Reset Synchronization
After power-up or reset, the PLL requires time before it achieves synchronization lock. The maximum time required for synchronization (TSYNC) is 500 ms.
Table 1. Frequency Mode Selection Feedback: Any Group A Output (Q4 - Q8)
Test 0 0 0 0 Select Pins F0 1 0 0 1 F1 0 0 1 1 Mode /4 /5 /6 Not Used Reference Clock Frequency Range 70 MHz - 105 MHz 56 MHz - 84 MHz 48 MHz - 70 MHz N.A. Output Frequency Range Group A: Q4-Q8 B: Q0-Q3, C: Q9-Q10 70 MHz - 105 MHz 35 MHz - 52 MHz 1 56 MHz - 84 MHz 28 MHz - 42 MHz 48 MHz - 70 MHz 24 MHz - 35 MHz N.A. N.A.
Feedback: Any Group B Output (Q0 - Q3)
Test 0 0 0 0
Note:
Select Pins F0 1 0 0 1
F1 0 0 1 1
Mode /8 / 10 / 12 Not Used
Reference Clock Frequency Range 35 MHz - 52 MHz 28 MHz - 42 MHz 24 MHz - 35 MHz N.A.
Output Frequency Range Group A: Q4-Q8 B: Q0-Q3, C: Q9-Q10 70 MHz - 105 MHz 35 MHz - 52 MHz 1 56 MHz - 84 MHz 28 MHz - 42 MHz 48 MHz - 70 MHz 24 MHz - 35 MHz N.A. N.A.
1. This mode produces outputs with 40/60 duty cycle for Q4 - Q8 only.
2
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GA1085
Table 2. Phase Shift Selection
S0 0
0 1 1
S1 0
1 0 1
Phase Difference (Q9, Q10) +2t
+t -t -2t
Table 3. Test Mode Selection
Test
1 1 1 1
F0
1 0 0 1
F1
0 0 1 1
Mode
/4 /5 /6 --
Ref. Clock
f REF f REF f REF --
Group A: Outputs Q4-Q8
f REF / 4 f REF / 5 f REF / 6 --
Groups B, C: Q0-Q3, Q9, Q10
f REF / 8 f REF / 10 f REF / 12 --
Multiple ground and power pins on the GA1085 reduce ground bounce. Good layout techniques, however, are necessary to guarantee proper operation and to meet the specifications across the full operating range. TriQuint recommends bypassing each of the VDD supply pins to the nearest ground pin, as close to the chip as possible. Figure 2 shows the recommended power layout for the GA1085. The bypass capacitors should be located on the same side of the board as the GA1085. The VDD traces connect to an inner-layer VDD plane. All of the ground pins (GND) are connected to a small ground plane on the surface beneath the chip. Multiple through-holes connect this small surface plane to an inner-layer ground plane. The capacitors (C1-C5) are 0.1 F. TriQuint's test board uses X7R temperaturestable capacitors in 1206 SMD cases.
Figure 2. Top Layer Layout of Power Pins (magnified approximately 3.3x)
V DD C4
Pin 1
V DD C3
Ground Plane
V DD C2
C5 V DD V DD
Pin 15
C1
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3
SYSTEM TIMING SYSTEM TIMING PRODUCTS
Layout Guidelines
GA1085
Absolute Maximum Ratings1
Storage temperature Ambient temperature with power applied 2 Supply voltage to ground potential DC input voltage DC input current Package thermal resistance (MQuad) Die junction temperature
-65 C to +150 C -55 C to +100 C -0.5 V to +7.0 V -0.5 V to (VDD + 0.5) V -30 mA to +5 mA JA = 45 C/W TJ = 150 C
DC Characteristics (VDD = +5 V + 5%, TA = 0 C to +70 C)
Symbol
VOHT VOHC VOL VIH 4 VIL4 IIL IIH II IDDS5 VI
Description
Output HIGH voltage Output HIGH voltage Output LOW voltage Input HIGH level Input LOW level Input LOW current Input HIGH current Input HIGH current Power supply current Input clamp voltage
Test Conditions
VDD = Min IOH = -30 mA VIN = VIH or VIL VDD = Min IOH = -1 mA VIN = VIH or VIL VDD = Min IOL = 30 mA VIN = VIH or VIL Guaranteed input logical HIGH voltage for all Inputs Guaranteed input logical LOW voltage for all inputs VDD = Max VIN = 0.40 V VDD = Max VIN = 2.7 V VDD = Max VIN = 5.5 V VDD = Max VDD = Min IIN = -18 mA
Min3
2.4 3.2
Typ
3.4 4.1 0.27
Max3
Unit
V V
0.5
V V
2.0 0.8 -156 0 2 119 -0.70 -400 25 1000 160 -1.2
V A A A mA V
Capacitance
Symbol
CIN
6
Description
Input capacitance
Test Conditions
VIN = 2.0 V at f = 1 MHz
Min
Typ
6
Max
Unit
pF
Notes:
1. Exceeding these parameters may damage the device. 2. Maximum ambient temperature with device not switching and unloaded. 3. Typical limits are at VDD = 5.0 V and TA = 25 C. 4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 5. This parameter is measured with device not switching and unloaded. 6. These parameters are not 100% tested, but are periodically sampled.
4
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GA1085
AC Characteristics
Symbol
tCPWH tCPWL tIR
(VDD = +5 V + 5%, TA = 0 C to +70 C)
Test Conditions (Figure 3)1
Figure 4 Figure 4
Input Clock (REFCLK)
CLK pulse width HIGH CLK pulse width LOW Input rise time (0.8 V - 2.0 V)
Min Typ
3 3 -- ------
Max
-- -- 2.0
Unit
ns ns ns
Output Clocks (Q0-Q10)
tOR, tOF tPD2 tSKEW13 tSKEW23 tSKEW33 tSKEW43 tCYC4 tJP5 tJR5 tSYNC6
Notes:
Rise/fall time (0.8 V-2.0 V) CLK I to FBIN I (GA1085-MC1000) Rise-rise, fall-fall (within group) Rise-rise, fall-fall (group-to-group, aligned) Rise-rise, fall-fall (group-to-group, non-aligned) Rise-fall, fall-rise Duty-cycle Variation Period-to-Period Jitter Random Jitter Synchronization Time
Figure 4 Figure 4 Figure 5 Figure 6 (skew2 takes into account skew1)
350 -- 1400 -1350-350 +650 -- -- 60 75 150 350 650 1200 +1000 200 400 500
ps ps ps ps ps ps ps ps ps s
SYSTEM TIMING SYSTEM TIMING PRODUCTS
Figure 7 ---- (skew3 takes into account skew1, skew2) Figure 8 ---- (skew4 takes into account skew3) Figure 4 -1000 0 Figure 4 Figure 4 -- 80 -- 190 -- 10
1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V). 2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN. 3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V. 4. This specification represents the deviation from 50/50 on the outputs. 5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock. tJP is the jitter on the output with respect to the output's previous rising edge. 6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
+5 V R1 R2 Z FBIN Q0 Q1 Q2 * * * * Q10 Y 50 X +5 V R1 R2 * * * * +5 V R1 R2 +5 V R1 R2 Notes: R1 = 160 R2 = 71 Y+Z=X
+5 V R1 R2 Z CLK
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5
GA1085
Switching Waveforms
Figure 3. General Timing
tCPW REFCLK tCPW
Figure 6. tSKEW3 (For Group B Feedback)
f = 2x f REF
Period = 1 f REFCLK
t PD1,2 FBIN
t JR
Group A
t1 t SKEW3 =
Period - t1 2
Q0 - Q10 (INDIVIDUALLY)
t PERIOD t JP
(For Group A or B Feedback)
Group A t4 Group C t SKEW3 = n - t4
Figure 4. tSKEW1
Group A Group A t SKEW1 Group B Group B t SKEW1 Group C Group C t SKEW1 t SKEW1 t SKEW1 t SKEW1
Group B t4 Group C t SKEW3 = n - t4
Note:"n" is the phase-shift increment: 2t, t, -t, -2t.
Figure 7. tSKEW4
f = f REF
Groups B, C Period = 1 f REFCLK
f = 2x f REF
Group A
t2
t3
t4 Period - t3 = 4 Period - t4 4
Figure 5. tSKEW2
Group B
t SKEW4 =
Period - t2 = 2
Group A t SKEW2
6
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GA1085
28-Pin MQuad J-Leaded Package Mechanical Specification (All dimensions are in inches)
.172 .005 .490 .005 .045 X 45 .445 .005 .132 .005 .040 MIN
PIN 1 8 0.125 VENT PLUG 15 .015 X 45 22
.490 .005 .445 .005 .445 .028 .005 .018
.410 .015
.050 TYP. .060
.050 TYP. NON-ACCUM.
.104 .005
28-Pin MQuad Pin Description
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name
GND Q9 Q10 VDD GND F0 F1 S0 REFCLK S1 FBIN TEST VDD Q0
Description
Ground Output Clock 9 (C1) Output Clock 10 (C2) +5 V Ground Frequency Select 0 Frequency Select 1 Shift Select 0 Reference Clock Shift Select 1 Feedback In Test +5 V Output Clock 0 (B1)
I/O
-- O O -- -- I I I I I I I -- O
Pin #
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name
GND Q1 Q2 VDD GND Q3 Q4 VDD Q5 Q6 GND VDD Q7 Q8
Description
Ground Output Clock 1 (B2) Output Clock 2 (B3) +5 V Ground Output Clock 3 (B4) Output Clock 4 (A1) +5 V Output Clock 5 (A2) Output Clock 6 (A3) Ground +5 V Output Clock 7 (A4) Output Clock 8 (A5)
I/O
-- O O -- -- O O -- O O -- -- O O
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7
SYSTEM TIMING SYSTEM TIMING PRODUCTS
GA1085
Output Characteristics
The IV characteristics, transition times, package characteristics, device and bond-wire characteristics for the GA1085 are described in Tables 4 through 9 and Figures 9 through 11. These output characteristics are provided for modelling purposes only. TriQuint does not guarantee the information in these tables and figures.
Figure 9. IOH vs.VOH
HIGH
0 -20 -40 0.0 1.0 2.0 3.0 4.0 5.0
VOH min VOH max
Figure 10. IOL vs.VOL
LOW
160 140 120
VOL min VOL max
IOH (mA)
IOL (mA)
Volts
-60 -80 -100 -120 -140 -160
100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 5.0
Volts
Table 4. IOH vs.VOH
VOH
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.0 7.0 8.0 9.0 10.0
Table 5. IOL vs.VOL
IOH max (mA)
-160 -157 -152 -142 -130 -106 -79 -42 0 0 0 0 0 0 1 5
IOH min (mA)
-70 -70 -68 -65 -59 -48 -29 0 0 0 0 0 0 0 0 0
VOL
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10.0
Notes:
IOL min (mA)
-145 -135 -115 -90 -40 0 37 49 53 54 54 54 54 54 54 54 54
IOL max (mA)
-435 -410 -350 -265 -120 0 97 140 155 157 159 160 160 160 160 160 160
1. These are worst-case corners for process, voltage, and temperature. 2. Includes diode to ground current.
8
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GA1085
Table 6. Characteristics Above VDD and Below Ground
Table 9. Rise and Fall Times (Into 0 pF, 50 Ohms to 1.5 V)
Time (ns) TR min (V) TR max (V) TF min (V) TF max (V)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 0.15 0.15 0.16 0.18 0.23 0.26 0.34 0.46 0.67 0.89 1.12 1.32 1.50 1.73 1.93 2.15 2.75 2.58 2.75 2.90 3.02 3.12 3.17 3.19 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.34 0.39 0.49 0.63 0.86 1.09 1.27 1.45 1.64 2.23 2.00 2.23 2.41 2.50 2.64 2.77 2.86 2.95 2.99 3.02 3.02 3.04 3.04 3.04 3.04 3.04 3.04 3.04 3.04 3.20 3.20 3.06 2.86 2.62 2.38 2.17 2.00 1.85 1.69 1.52 1.38 1.26 1.12 0.96 0.83 0.52 0.61 0.52 0.45 0.39 0.33 0.29 0.24 0.21 0.19 0.17 0.16 0.16 0.15 0.15 0.15 0.15 0.15 0.15 0.15 3.04 3.04 2.95 2.90 2.68 2.50 2.36 2.22 2.09 1.95 1.86 1.68 1.59 1.49 1.36 1.23
SYSTEM TIMING SYSTEM TIMING PRODUCTS
V
Diode to GND I (mA)
0 0 0 -5 -15 -35 -55 -75 -300 -350 -360
Diode Stack to VDD V I (mA)
5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 0 0 0 0 0 1 5 9
0.0 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -2.0 -2.5 -3.0
Note: TriQuint does not guarantee diode operation for purposes other than ESD protection.
Figure 11. Output Model
L1 DIE C1 C2 L2 OUTPUT
0.95 1.00 0.95 0.91 0.86 0.77 0.73 0.68 0.64 0.59 0.55 0.53 0.50 0.45 0.41 0.40 0.37 0.36 0.32 0.32
Table 7. Device and Bond-Wire Characteristics (Estimates)
L1
2 nH
C1
10 pF
Table 8. 28-Pin MQuad Package Characteristics
L2
1.85 nH
C2
0.40 pF
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9
GA1085
Ordering Information
To order, please specify as shown below:
GA1085-MC nnnn
11-Output Configurable Clock Buffer
Propagation delay skew: 1000 = -350 ps 1000 ps Temperature range: Commercial (0 C to 70 C) Package: MQuad
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
10
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